SH7763 Datasheet, PDF (332/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
UIMASK level are held disabled, and correct operation may not be performed (for example, the
OS cannot switch tasks).
An example of the usage procedure is shown below.
1. Classify interrupts to A and B as described below and set the A priority higher than the B
priority.
A. Interrupts to be accepted in the device driver (interrupts to be used by the operating system:
a timer interrupt etc.)
B. Interrupts to be disabled in the device driver
2. Make the MMU settings so that the address space including USERIMASK can only be
accessed by the device driver in which interrupts should be disabled.
3. Branch to the device driver.
4. Set the UIMASK bit to mask B interrupts in the device driver that is operating in user mode.
5. Process interrupts with high priority in the device driver.
6. Clear the UIMASK bit to 0 to return from processing in the device driver.
9.3.13 On-chip module Interrupt Priority Registers (INT2PRI0 to INT2PRI13)
INT2PRI0 to INT2PRI13 are 32-bit readable/writable registers that set priorities (levels 31 to 0) of
the on-chip peripheral module interrupts. INT2PRI0 to INT2PRI13 are initialized to H'0000 0000
by a reset.
INT2PRI0 to INT2PRI13 can set 30 priority levels (32 types of interrupt requests) to individual
interrupt sources with five bits (interrupt requests are masked at H'00 and H'01).
Bit:
Initial value:
R/W:
Bit:
Initial value:
R/W:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
−− −
−− −
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R R R R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W
15 14 13 12 11 10 9
−− −
8
7
6
−−
0
0
0
0
0
0
0
0
0
0
R R R R/W R/W R/W R/W R/W R R
5
4
3
2
1
0
−
0
0
0
0
0
0
R R/W R/W R/W R/W R/W
Rev. 1.00 Oct. 01, 2007 Page 266 of 1956
REJ09B0256-0100