SH7763 Datasheet, PDF (906/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.28 Burst Cycle Count Upper-Limit Register (BCULR)
BCULR sets the upper limit for the number of burst cycles.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
















Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0




BSTLMT[11:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
31 to 12
11 to 0
Bit Name

Initial
Value
All 0
BSTLMT[11:0] All 0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Burst Cycle Upper-Limit
These bits set the upper limit for burst cycles. Burst
transfer is finished when the burst timer exceeds the
value set in this register. If the burst timer exceeds the
value set in this register while a frame is being
transferred, burst transfer is continued until transfer of
the corresponding frame is completed.
H'000 to H'100: Burst cycle count is 256 cycles
H'101: Burst cycle count is 257 cycles
:
:
H'FFE: Burst cycle count is 4,094 cycles
H'FFF: Burst cycle count is 4,095 cycles
Note: 1 cycle = 32 ns
Rev. 1.00 Oct. 01, 2007 Page 840 of 1956
REJ09B0256-0100