SH7763 Datasheet, PDF (1020/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
(4) Descriptor Pointer
The E-DMAC controls the transmit and receive descriptor addresses in memory and the
processing priority by using the following registers.
1. Registers related to a transmit descriptor
• TDLAR: Address of the start descriptor in a list of transmit descriptors.
• TDFAR: Address of the transmit descriptor to be processed
• TDFXR: Address of the transmit descriptor that finished processing (set by a write-back
operation) last
• TDFFR (DL bit): Indicates whether the TDLE value of the transmit descriptor specified by
TDFXR is 1 or not.
2. Registers related to receive descriptor:
• RDLAR: Address of the start descriptor in a list of receive descriptors.
• RDFAR: Address of the receive descriptor to be processed
• RDFXR: Address of the receive descriptor that finished processing (set by a write-back
operation) last
• RDFFR (DL bit): Indicates whether the RDLE value of the receive descriptor specified by
RDFXR is 1 or not.
Transmit descriptors and receive descriptors have a ring structure. When the TDLE (RDLE) value
of the processed transmit (receive) descriptor is 0, the next descriptor will be processed. The next
descriptor is the transmit (receive) descriptor at the address obtained by adding the processed
transmit (receive) descriptor address to the descriptor length specified by the DL bit in EDMR.
When the TDLE (RDLE) value of the processed transmit (receive) descriptor is 1, the transmit
descriptor indicated by TDLAR (RDLAR) will be processed next. Figure 23.7 shows the
relationship between the transmit/receive descriptor ring and read pointer.
The transmit descriptor list must be large enough to point to five or more transmit frames. If four
or less transmit frames are pointed to in a list, E-DMAC operation is not guaranteed. Accordingly,
do not set that all the transmit descriptors in a ring are used by four or less descriptors. The receive
descriptor list does not have this restriction. For example, one receive frame can use all receive
descriptors in a list.
In the initial setting, the start address of a descriptor list must be set to TDLAR (RDLAR) and
TDFAR (RDFAR), and the end descriptor address of the descriptor list to TDFXR (RDFXR) by
the software.
The E-DMAC updates TDFAR (RDFAR), TDFXR (RDFXR) and the DL bit in TDFFR (DL bit in
RDFFR) each time a descriptor is processed.
Rev. 1.00 Oct. 01, 2007 Page 954 of 1956
REJ09B0256-0100