SH7763 Datasheet, PDF(482/2026 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

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SH7763 Datasheet, PDF (482/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

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Section 12 DDR-SDRAM Interface (DDRIF)

Table 12.5 Register State in Each Operating Mode

Register Name

Power-On Manual

Abbreviation Reset

Reset

Sleep

Standby

Memory interface mode

MIM

register

H'0000 0000 H'0000 0000 Retained Retained

0C34 xx00*1 0C34 xx00*1

DDR-SDRAM control register SCR

H'0000 0000 H'0000 0000 Retained Retained

0000 0000 0000 0000

DDR-SDRAM timing register STR

H'0000 0000 H'0000 0000 Retained Retained

0000 0000 0000 0000

DDR-SDRAM row attribute

register

SDR

H'0000 0000 H'0000 0000 Retained Retained

0000 0100 0000 0100

DDR-SDRAM mode register SDMR

Only writing Only writing Only

writing

Only

writing

DDR-SDRAM back-up register DBK

H'0000 0000 H'0000 0000 Retained Retained

0000 000x*2 0000 000x*2

Notes: 1. The initial value of bit 8 (ENDIAN bit) depends on the setting of external pins (MD5).

2. The initial value of bit 0 (SDBUP bit) depends on the setting of external pin

(M_BKPRST).

All bits are active-high signals and are initialized by a reset unless otherwise specified.

All access is made in longwords using the SuperHyway bus.

Rev. 1.00 Oct. 01, 2007 Page 416 of 1956

REJ09B0256-0100

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