SH7763 Datasheet, PDF (1792/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 40 General Purpose I/O (GPIO)
40.2.21 Port F Data Register (PFDR)
PFDR is an 8-bit readable/writable register that stores port F data.
Bit: 7
6
5
4
3
2
1
0
—
—
—
— PF3DT PF2DT PF1DT PF0DT
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R/W R/W R/W R/W
Initial
Bit
Bit Name value R/W Description
7 to 4 
All0
R
Reserved
These bits are always read as 0, and the write value
should always be 0.
3
PF3DT
0
R/W Each of these bits stores output data for the
2
PF2DT
0
R/W ^{corresponding pin that is used as a general output port.}
If the port is read, the value of the corresponding bit in
1
PF1DT
0
R/W _{this register will be read for a pin configured as a}
0
PF0DT
0
R/W ^{general output port, while the state of the}
corresponding pin will be read for a pin configured as a
general input port.
Rev. 1.00 Oct. 01, 2007 Page 1726 of 1956
REJ09B0256-0100