SH7763 Datasheet, PDF (681/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 14 Direct Memory Access Controller (DMAC)
14.5.4 DACK and TEND Output Divisions
The DACK and TEND output are divided to align the data unit like the CSn output when a DMA
transfer unit is divided with multiple bus cycles, for example when an 8-bit or 16-bit external
device is accessed in longword units, or when an 8-bit external device is accessed in word units,
and the CSn output is negated between these bus cycles.
14.5.5 CS Output Settings and Transfer Size Larger than External Bus Width
When one DMA transfer is performed by multiple bus cycles*¹, the CSn output should be set not
to negate between bus cycles*². For detail of settings, refer to tables 11.9 to 11.14. If set the CSn
output is negated between bus cycles, the DREQ signal is not sampled correctly and malfunction
may occur.
Notes: 1. When a DMA transfer is performed with larger transfer size than the bus width. For
example, performing the 16-/32-byte transfer to the 8-/16-/32-bit bus width LBSC
space, longword (32-bit) transfer to the 8-/16-bit bus width LBSC space, or word (16-
bit) transfer to the 8-bit bus width LBSC space. Note that except for a 32-bit access to
the MPX interface. This access generates only one bus cycle (burst).
2. When the CSn output is negated between bus cycles, then the DACK output is also
negated between bus cycles (DACK output is also divided).
14.5.6 DACK and TEND Assertion and DREQ Sampling
The DACK and TEND signals may be asserted ceaselessly during two or more times DMA
transfer when the DREQ level detection with overrun 1 and the DREQ edge detection. In this case,
the DMA transfer is suspended and do not perform correctly, to avoid this insert one or more idle
cycle between the DMA transfer.
The transfer source is the LBSC space and the DACK and TEND are output during the read cycle:
(1) Set B'001 to B'111 (i.e., other than 000) to the IWRRD bits in CSnBCR
(2) Set B'001 to B'111 (i.e., other than 000) to the IWRRS bits in CSnBCR
Rev. 1.00 Oct. 01, 2007 Page 615 of 1956
REJ09B0256-0100