SH7763 Datasheet, PDF (1215/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
Baud Rate
4800
7200
9600
14400
19200
38400
76800
115200
Note: * : Error rate = 0
Division Ratio
48
32
24
16
12
6
3
2
Error Rate*








28.3.14 BRG Clock Select Register (BRGCKS2)
BRGCKS2 switches output clock between the division clock generated by the BRG and
the external clock (SCIF2_SCK).
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BRG
CKS















Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R R R R R R R R R R R R R R R
Initial
Bit
Bit Name Value
15
BRGCKS 0
14 to 0 
All 0
R/W Description
R/W Switches output clock between the division clock and
external clock (SCIF2_SCK).
0: Selects division clock
1: Selects external clock
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1149 of 1956
REJ09B0256-0100