SH7763 Datasheet, PDF (1022/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.4.2 Transmission
(1) Transmission Procedure and Processing Flow
When 11 is written to the TR bits in EDTRR with the TE bit in ECMR set to 1 and there is empty
space of 32 bytes or more in the transmit FIFO, the E-DMAC reads the descriptor following the
previously used descriptor from the transmit descriptor list (or the descriptor indicated by TDLAR
at the initial startup).
If the TACT bit of the read descriptor is set to 1 (valid), the E-DMAC sequentially reads transmit
frame data from the transmit buffer start address specified by TD2 and transfers the data to the
transmit FIFO. The E-DMAC configures a transmit frame and starts transmission to the
GMII/MII/RMII. After DMA transfer of data equivalent to the buffer length specified in the
descriptor, the following processing is carried out according to the TFP value.
• TFP = 10 (start of a frame)
Descriptor write-back (writing 0 to the TACT bit) is performed after completion of DMA
transfer.
• TFP = 01 or 11 (end of a frame)
Descriptor write-back (writing 0 to the TACT bit and writing status) is performed after
completion of frame transmission.
• TFP = 00 (frame continued)
Descriptor write-back is not performed. The TACT bit retains the value 1.
As long as the TACT bit of a read descriptor is set to 1 (valid), the reading of E-DMAC
descriptors and the transmission of frames continue.
When a descriptor with the TACT bit cleared to 0 (invalid) is read, the E-DMAC performs the
following processing and completes transmit processing.
• Clears the TR bits in EDTRR to 00.
• Writes the TC bits in EESR to 11 and generates an interrupt to the CPU.
The E-DMAC can store up to four frames of data in the transmit FIFO.
Rev. 1.00 Oct. 01, 2007 Page 956 of 1956
REJ09B0256-0100