SH7763 Datasheet, PDF (284/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 8 L Memory
8.2 Register Descriptions
The following registers are related to L memory.
Table 8.2 Register Configuration
Name
Area 7
Abbreviation R/W P4 Address* Address*
Access Size
On-chip memory control RAMCR
register
R/W H'FF000074 H'1F000074 32
L memory transfer source LSA0
address register 0
R/W H'FF000050 H'1F000050 32
L memory transfer source LSA1
address register 1
R/W H'FF000054 H'1F000054 32
L memory transfer
destination address
register 0
LDA0
R/W H'FF000058 H'1F000058 32
L memory transfer
destination address
register 1
LDA1
R/W H'FF00005C H'1F00005C 32
Note: * The P4 address is the address used when using P4 area in the virtual address space.
The area 7 address is the address used when accessing from area 7 in the physical
address space using the TLB.
Rev. 1.00 Oct. 01, 2007 Page 218 of 1956
REJ09B0256-0100