SH7763 Datasheet, PDF (979/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
Initial
Bit
Bit Name Value R/W Description
20
TDE
0
R/W Transmit Descriptor Empty
Indicates that the transmit descriptor valid bit (TACT) of
a transmit descriptor read by the E-DMAC is not set if
the previous descriptor does not represent the end of a
frame in multi-buffer frame processing based on single-
frame/multi-descriptor operation. As a result, an
incomplete frame may be sent.
0: Transmit descriptor active bit TACT = 1 detected
1: Transmit descriptor active bit TACT = 0 detected
When transmit descriptor empty (TDE = 1) occurs,
execute a software reset and initiate transmission. In
this case, transmission starts from the address that is
stored in the transmit descriptor list start address
register (TDLAR).
19
TFUF
0
R/W Transmit FIFO Underflow
Indicates that an underflow has occurred in the transmit
FIFO during frame transmission. Incomplete data is
sent onto the line.
0: Underflow has not occurred
1: Underflow has occurred
18
FR
0
R/W Frame Reception
Indicates that a frame has been received and the
receive descriptor has been updated. This bit is set to 1
each time a frame is received.
0: Frame has not been received
1: Frame has been received
17
RDE
0
R/W Receive Descriptor Empty
Indicates that the RACT bit of a receive descriptor read
by the E-DMAC for receive DMA operation is cleared to
0 (invalid).
When receive descriptor empty (RDE = 1) occurs,
reception can be resumed by setting the RACT bit
(cleared to 0) of the receive descriptor to 1 and then
writing 1 to the RR bit in EDRRR.
0: Receive descriptor active bit RACT = 1 detected
1: Receive descriptor active bit RACT = 0 detected
Rev. 1.00 Oct. 01, 2007 Page 913 of 1956
REJ09B0256-0100