SH7763 Datasheet, PDF (1864/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 42 User Debugging Interface (H-UDI)
ASEBRK/BRKACK
Break controller
Boundary-scan
TAP controller
Interrupt/reset etc
TCK
TMS
TRST
SDBSR
SDBPR
TAP controller
Decoder
TDI
TDO
SDIR
SDINT
[Legend]
SDBPR:
SDBSR:
SDINT:
SDIR:
Bypass register
Boundary scan register
Interrupt source register
Instruction register
Figure 42.1 H-UDI Block Diagram
Rev. 1.00 Oct. 01, 2007 Page 1798 of 1956
REJ09B0256-0100