SH7763 Datasheet, PDF (1629/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

• Data Stage (Control-Out)
USB function
OUT token reception
Section 36 USB Function Controller (USBF)
Application
1 written
to TRG/EP0s
RDFN?
Yes
No
NAK
Data reception from host
ACK
Set EP0o reception
complete flag
(IFR0/EP0o TS = 1)
Interrupt request
OUT token reception
1 written
to TRG/EP0o
RDFN?
Yes
No
NAK
Clear EP0o reception
complete flag
(IFR0/EP0o TS = 0)
Read data from EP0o
receive data size register
(EPSZ0o)
Read data from EP0o
data register (EPDR0o)
Write 1 to EP0o read
complete bit
(TRG/EP0o RDFN = 1)
Figure 36.7 Data Stage (Control-Out) Operation
The application first analyzes command data from the host in the setup stage, and determines the
subsequent data stage direction. If the result of command data analysis is that the data stage is out-
transfer, the application waits for data from the host, and after data is received (IFR0/EP0o TS =
1), reads data from the FIFO. Next, the application writes 1 to the EP0o read complete bit, empties
the receive FIFO, and waits for reception of the next data.
The end of the data stage is identified when the host transmits an IN token and the status stage is
entered.
Rev. 1.00 Oct. 01, 2007 Page 1563 of 1956
REJ09B0256-0100