SH7763 Datasheet, PDF (297/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 8 L Memory
When the OCBWB instruction is issued to the L memory area, the physical address bits [28:10]
are generated in accordance with the LDA0 or LDA1 specification. The physical address bits [9:5]
are generated from the virtual address. The physical address bits [4:0] are fixed to 0. Block
transfer is performed from the L memory to the external memory specified by these physical
addresses.
8.4 L Memory Protective Functions
This LSI implements the following protective functions to the L memory by using the on-chip
memory access mode bit (RMD) and the on-chip memory protection enable bit (RP) in the on-chip
memory control register (RAMCR).
• Protective functions for access from the CPU and FPU
When RAMCR.RMD = 0, and the L memory is accessed in user mode, it is determined to be
an address error exception.
When MMUCR.AT = 1 and RAMCR.RP = 1, MMU exception and address error exception are
checked in the L memory area which is a part of P4 area as with the area P0/P3/U0.
The above descriptions are summarized in table 8.4.
Table 8.4 Protective Function Exceptions to Access L Memory
MMUCR.AT RAMCR.RP SR.MD RAMCR. RMD
0
*
0
0
1
1
*
1
0
0
0
1
1
*
1
0
0
1
1
*
Note: * Don't care
Always Occurring
Exceptions
Address error
exception
—
—
Address error
exception
—
—
Address error
exception
—
—
Possibly Occurring
Exceptions
—
—
—
—
—
—
—
MMU exception
MMU exception
Rev. 1.00 Oct. 01, 2007 Page 231 of 1956
REJ09B0256-0100