SH7763 Datasheet, PDF (1247/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
28.6 Baud Rate Generator for External Clock (BRG)
The baud rate generator for external clock (hereafter abbreviated as BRG) is included in the
SCIF/IrDA and supplies the IrDA block with a sampling clock (BRGCLK), which is derived from
the external clock (SCIF_CLK) or internal clock (Pck0) divided by the division ratio from 1
through 2 to the sixteenth power minus 1.
28.6.1 BRG Block Diagram
Figure 28.23 shows a block diagram of the BRG.
IO-BUS IF
reset_brg
Infrared data
Communication
Inteface (IrDA)
BRGCLK
Reset controler
Trigger generator
SCIF_SCK
Control register
Base counter
BRG block
SCIF/IrDA
SC_CLK
(selected from
among SCIF_CLK
and Pck0)
Figure 28.23 BRG Block Diagram
Rev. 1.00 Oct. 01, 2007 Page 1181 of 1956
REJ09B0256-0100