SH7763 Datasheet, PDF (1248/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
(1) Reset controller
The reset controller controls resetting of the control register, base counter, and trigger generator.
(2) Control register
The control register has the frequency division register and clock select register.
For details, see section 28.3, Register Descriptions.
(3) Base counter
The base counter is a 16-bit CLK (external clock BRG input) synchronization counter.
This counter is used to determine timing of a frequency divided clock when it is generated.
(4) Trigger generator
The trigger generator generates rising-edge/falling-edge triggers for a frequency divided clock,
taking timing according to values of the frequency division register and base counter. The triggers
generate the frequency divided clock.
The trigger generator also switches the output between SCIF2_CLK (external clock input) and the
frequency divided clock.
28.6.2 Restrictions on the BRG
(1) Notes on Frequency Division Register Settings
1. At the first setting of BSGDL2 after a reset, wait time of one bit period or more is required to
ensure the clock settling time.
(Example) Period of one bit when BSGDL2 = 2
3.68 (MHz) × 1/2 × 1/16 = 0.115 (MHz) → 8695 (ns)
2. After the setting stated in 1 above, wait time of one bit period or more is required at the
maximum bit rate (BSGDL2 = 65535) before the value of BSGDL2 is changed again.
Rev. 1.00 Oct. 01, 2007 Page 1182 of 1956
REJ09B0256-0100