SH7763 Datasheet, PDF (199/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 5 Exception Handling
(2) General Interrupt Request
• Source: The interrupt mask level bits setting in SR is smaller than the interrupt level of
interrupt request, and the BL bit in SR is 0 (accepted at instruction boundary).
• Transition address: VBR + H'00000600
• Transition operations:
The PC contents immediately after the instruction at which the interrupt is accepted are set in
SPC. The SR and R15 contents at the time of acceptance are set in SSR and SGR.
The code corresponding to the each interrupt source is set in INTEVT. The BL, MD, and RB
bits are set to 1 in SR, and a branch is made to VBR + H'0600.
Module_interruption()
{
SPC = PC;
SSR = SR;
SGR = R15;
INTEVT = H'0000 0400 ~ H'0000 3FE0;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
if (cond) SR.IMASK = level_of accepted_interrupt ();
PC = VBR + H'0000 0600;
}
5.6.4 Priority Order with Multiple Exceptions
With some instructions, such as instructions that make two accesses to memory, and the
indivisible pair comprising a delayed branch instruction and delay slot instruction, multiple
exceptions occur. Care is required in these cases, as the exception priority order differs from the
normal order.
• Instructions that make two accesses to memory
Rev. 1.00 Oct. 01, 2007 Page 133 of 1956
REJ09B0256-0100