SH7763 Datasheet, PDF (1635/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

36.4.5 EP3 Interrupt-In Transfer
USB function
Section 36 USB Function Controller (USBF)
Application
IN token reception
Valid data
in EP3 FIFO?
Yes
No
NAK
Data transmission to host
ACK
Is there data
No
for transmission
to host?
Yes
Write data to EP3 data
register (EPDR3)
Write 1 to EP3 packet
enable bit
(TRG/EP3 PKTE = 1)
Set EP3 transmission
complete flag
(IFR0/EP3 TS = 1)
Interrupt request
Clear EP3 transmission
complete flag
(IFR1/EP3 TS = 0)
Is there data
No
for transmission
to host?
Yes
Write data to EP3 data
register (EPDR3)
Write 1 to EP3 packet
enable bit
(TRG/EP3 PKTE = 1)
Note: This flowchart shows just one example of interrupt transfer processing. Other possibilities include an
operation flow in which, if there is data to be transferred, the EP3 DE bit in the USB data status register
is referenced to confirm that the FIFO is empty, and then data is written to the FIFO.
Figure 36.12 EP3 Interrupt-In Transfer Operation
Rev. 1.00 Oct. 01, 2007 Page 1569 of 1956
REJ09B0256-0100