SH7763 Datasheet, PDF (1095/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 26 I²C Bus Interface (IIC)
26.3.1 Slave Control Register (ICSCR)
Bit: 7
−
Initial value: 0
R/W: R
6
5
−−
0
0
RR
4
3
2
1
0
− SDBS SIE GCAE FNA
0
0
0
0
0
R R/W R/W R/W R/W
Bit
7 to 4
3
2
1
Bit Name Initial Value R/W
—
All 0
R
SDBS
0
R/W
SIE
0
R/W
GCAE
0
R/W
Description
Reserved
The write value should always be 0.
Slave Data Buffer Select
This bit is used to select the data buffer. The
double-buffer mode and single-buffer mode are
available.
When this bit is set to 0, the double-buffer mode
is selected. During a reception, as long as both
buffers are full and the SDR flag has not been
cleared, SCL is held low. When the SDR flag is
cleared, the low level state of SCL is released.
When this bit is set to 1, the single-buffer mode is
selected. SCL will be held low from the timing
when the receive data register acquires the data
packet until the SDR flag is cleared.
0: Double-buffer mode
1: Single-buffer mode
Slave Interface Enable
This bit must be set for the slave operation. If this
bit is low, the slave interface is reset.
This bit is cleared by setting the MIE bit to 1.
General Call Acknowledgement Enable
When a master requires a slave to issue an
acknowledgement, this bit must be set to 1
Rev. 1.00 Oct. 01, 2007 Page 1029 of 1956
REJ09B0256-0100