SH7763 Datasheet, PDF (404/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 11 Local Bus State Controller (LBSC)
Initial
Bit
Bit Name Value
24
OPUP
0
23 to 20 DACKBST All 0
[3:0]
19, 18 
All 0
17
BREQEN 0
R/W Description
R/W Control Output Pin Pull-Up Resistor Control
Specifies the pull-up resistor state (A25 to A0, BS, CS0
to CS2, CS4, CS5/CE1A, CS6/CE1B, RD, WEn,
RDWR, CE2A, and CE2B) when the control output pins
are high-impedance. This bit is initialized by a power-on
reset.
0: Pull-up resistors are on for control output pins (A25 to
A0, BS, CS0 to CS2, CS4, CS5/CE1A, CS6/CE1B,
RD, WEn, RDWR, CE2A, and CE2B)
1: Pull-up resistors are off for control output pins (A25 to
A0, BS, CS0 to CS2, CS4, CS5/CE1A, CS6/CE1B,
RD, WEn, RDWR, CE2A, and CE2B)
Note: In standby mode, the control output pins are
pulled up, regardless of the bit setting.
R/W DACK Burst
Select assert period of DACKn signals of DMA burst
transfer mode during DMA transfer start to end.
0: DACKn signals does not keep assert from burst start
to end
1: DACKn signals keep assert from burst start to end
DACKBST[3]: DACK3
DACKBST[2]: DACK2
DACKBST[1]: DACK1
DACKBST[0]: DACK0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W BREQ Enable
Indicates whether or not an external bus request can be
accepted. This bit is initialized to the state where an
external bus request is not accepted at a power-on
reset.
0: An external bus request is not accepted
1: An external bus request is accepted
Rev. 1.00 Oct. 01, 2007 Page 338 of 1956
REJ09B0256-0100