SH7763 Datasheet, PDF (1170/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 27 Serial Communication Interface with FIFO (SCIF)
5. When modem control is enabled, the SCIF_RTS signal is output when SCFRDR is empty.
When SCIF0_RTS is 0, reception is possible. When SCIF_RTS is 1, this indicates that
SCFRDR contains bytes of data equal to or more than the SCIF_RTS output active trigger
number. The SCIF_RTS output active trigger value is specified by bits 10 to 8 in the FIFO
control register (SCFCR). For details, see section 27.3.9, FIFO control register (SCFCR). In
addition, SCIF_RTS is also 1 when the RE bit in SCSCR is cleared to 0.
Figure 27.14 shows an example of the operation when modem control is used.
Serial data
SCIF_RXD
Start
bit
0 D0 D1 D2
ParityStop
bit bit
D7 0/1 1
Start
bit
0
SCIF_RTS
Figure 27.14 Sample Operation Using Modem Control (SCIF0_RTS)
(Only in Channel 0)
27.4.3 Operation in Clocked Synchronous Mode
Clocked synchronous mode, in which data is transmitted or received in synchronization with clock
pulses, is suitable for fast serial communication.
Since the transmitter and receiver are independent units in the SCIF, full-duplex communication
can be achieved by sharing the clock. Both the transmitter and receiver have a 64-stage FIFO
buffer structure, so that data can be read or written during transmission or reception, enabling
continuous data transfer and reception.
Figure 27.15 shows the general format for clocked synchronous communication.
One unit of transfer data (character or frame)
*
Synchronization
clock
LSB
*
MSB
Serial data
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
Don't care
Don't care
Note: * High except in continuous transfer
Figure 27.15 Data Format in Clocked Synchronous Communication
Rev. 1.00 Oct. 01, 2007 Page 1104 of 1956
REJ09B0256-0100