SH7763 Datasheet, PDF (851/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.2 Input/Output Pins
Table 23.1 lists the pin configuration of the GETHER.
Table 23.1 Pin Configuration
Name
Port
Transmit clock 0
Transmit enable
MII/GMII
transmit data
GMII transmit
data
Collision
detection
Transmit error
Receive clock
Receive data
valid
MII/GMII receive
data
GMII receive
data
Receive error
Carrier detection
Management
data clock
Management
data I/O
Abbreviation
ET0_TX-CLK
I/O
Input
ET0_TX-EN
Output
ET0_ETXD3 to Output
ET0_ETXD0
GET0_ETXD7 to Output
GET0_ETXD4
ET0_COL
Input
Function
ET0_TX-EN, ET0_ETXD3 to
ET0_ETXD0, ET0_TX-ER timing
reference signal
Indicates that transmit data is ready on
ET0_ETXD3 to ET0_ETXD0
4-bit MII transmit data or lower four bits of
GMII transmit data
Upper four bits of GMII transmit data
Collision detection signal
ET0_TX-ER
ET0_RX-CLK
Output
Input
ET0_RX-DV
Input
ET0_ERXD3 to Input
ET0_ERXD0
GET0_ERXD7 to Input
GET0_ERXD4
ET0_RX-ER
Input
ET0_CRS
ET0_MDC
Input
Output
ET0_MDIO
I/O
Notifies PHY-LSI of error during
transmission
ET0_RX-DV, ET0_ERXD3 to
ET0_ERXD0, ET0_RX-ER timing
reference signal
Indicates that valid receive data is on
ET0_ERXD3 to ET0_ERXD0
4-bit MII receive data or lower four bits of
GMII receive data (MII and GMII)
Upper four bits of GMII receive data
Identifies error state occurred during data
reception
Carrier detection signal
Reference clock signal for information
transfer via ET0_MDIO
Bidirectional signal for exchange of
management information between STA
and PHY
Rev. 1.00 Oct. 01, 2007 Page 785 of 1956
REJ09B0256-0100