SH7763 Datasheet, PDF (1719/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

37.6 Usage Notes
Section 37 LCD Controller (LCDC)
37.6.1 Procedure for Halting Access to Display Data Storage VRAM (DDR-SDRAM in
Area 3)
Follow the procedure below to halt access to VRAM for storing display data (DDR-SDRAM in
area 3).
Procedure for Halting Access to Display Data Storage VRAM:
1. Confirm that the LPS1 and LPS0 bits in LDPMMR are currently set to 1.
2. Clear the DON bit in LDCNTR to 0 (display-off mode).
3. Confirm that the LPS1 and LPS0 bits in LDPMMR have changed to 0.
4. Wait for the display time for a single frame to elapse.
This halting procedure is required before selecting self-refreshing for the display data storage
VRAM (DDR-SDRAM in area 3) or making a transition to standby mode or module standby
mode.
37.6.2 Notes on Using NMI Interrupt
If the NMIFL bit in the NMIFCR register is set to 1 by an NMI interrupt while the LCDC is used,
the LCDC cannot access the VRAM that is used for the display data storage (DDR_SDRAM in
area 3).
As the LCDC continues to output data stored in the lime buffer to the LCD panel data pin, the
LCD display will be stopped if the line buffer becomes empty. Accordingly, NMI interrupts
should be disabled and he NMIFL bit should be cleared to 0 before the line buffer becomes empty.
Rev. 1.00 Oct. 01, 2007 Page 1653 of 1956
REJ09B0256-0100