SH7763 Datasheet, PDF (1029/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
lllegal carrrier
detection
RX-DV negation
ldle
RE set
Reception
halted
RE reset
Start of frame
reception
Premble
detection
Wait for SFD
reception
SFD
reception
Reset
Promiscuous and other
station destination address
Destination address
reception
Receive error
detection
Own destination address
or broadcast
or broadcast
or promiscuous
Error
notification*
Error
detection
Data
reception
Recevice error
decection
Legend
SFD: Start frame delimiter
Note: The error frame also transmits data to the buffer.
CRC
reception
Figure 23.10 E-MAC Receiver State Transitions
CAM evaluation can be referenced during frame processing in reception (for details on the CAM
function, refer to section 23.4.5, CAM Function).
When 1 is written to the RR bit in EDRRR while the RE bit in ECMR is set to 1, the E-DMAC
reads the descriptor following the previously used descriptor from the receive descriptor list (or
the descriptor indicated by RDLAR at the initial startup) then enters the receive wait state. If 32
bytes or more of data or the last byte of the receive frame is stored in the receive FIFO, the E-
DMAC transfers receive FIFO data to the receive buffer specified by RD2 according to the receive
descriptor with the RACT bit set to 1 (valid).
If the data length of a received frame is longer than the buffer length specified by RD1, the E-
DMAC performs a write-back operation to the descriptor (set RFP to 10 or 00) when the buffer is
full, then reads the next descriptor. The E-DMAC then continues to transfer data to the receive
buffer specified by the new RD2.
When the following conditions are satisfied, a write-back operation is performed for the descriptor
(RFP = 11 or 01), 11 is written to the FR bits in EESR, and an interrupt is issued to the CPU.
• The receive buffer has been full during DMA transfer.
• DMA transfer to the receive buffer of the last byte of the receive frame has been completed.
Rev. 1.00 Oct. 01, 2007 Page 963 of 1956
REJ09B0256-0100