SH7763 Datasheet, PDF (997/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.85 Transmit Descriptor Finished Address Register (TDFXR)
TDFXR stores the start address of the transmit descriptor for which the E-DMAC has just
completed the write-back processing. Up to which transmit descriptor has been processed by the
E-DMAC can be recognized by monitoring addresses displayed in this register. In the initial
setting, set the address of the transmit descriptor immediately before the descriptor that is pointed
to by the address in TDFAR.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
TDFX[31:16]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TDFX[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
31 to 0
Bit Name
TDFX[31:0]
Initial
Value R/W Description
All 0 R/W Transmit Descriptor Finished Address
Writing to these bits during transmission is prohibited.
Rev. 1.00 Oct. 01, 2007 Page 931 of 1956
REJ09B0256-0100