SH7763 Datasheet, PDF (1094/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 26 I²C Bus Interface (IIC)
Table 26.3 Register State in Each Operating Mode
Channel Register Name
0
Slave control register 0
Master control register 0
Slave status register 0
Master status register 0
Slave interrupt enable register 0
Master interrupt enable
register 0
Clock control register 0
Slave address register 0
Master address register 0
Receive data register 0
Transmit data register 0
1
Slave control register 1
Master control register 1
Slave status register 1
Master status register 1
Slave interrupt enable register 1
Master interrupt enable
register 1
Clock control register 1
Slave address register 1
Master address register 1
Receive data register 1
Transmit data register 1
Power-On Manual
Abbreviation Reset
Reset Sleep
Standby
ICSCR0 H'00
H'00 Retained Retained
ICMCR0 H'x0
H'x0 Retained Retained
ICSSR0 H'00
H'00 Retained Retained
ICMSR0 H'00
H'00 Retained Retained
ICSIER0 H'00
H'00 Retained Retained
ICMIER0 H'00
H'00 Retained Retained
ICCCR0
ICSAR0
ICMAR0
ICRXD0
ICTXD0
ICSCR1
ICMCR1
ICSSR1
ICMSR1
ICSIER1
ICMIER1
H'00
H'00
H'00
H'00
H'00
H'00
H'x0
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'x0
H'00
H'00
H'00
H'00
Retained Retained
Retained Retained
Retained Retained
Retained Retained
Retained Retained
Retained Retained
Retained Retained
Retained Retained
Retained Retained
Retained Retained
Retained Retained
ICCCR1
ICSAR1
ICMAR1
ICRXD1
ICTXD1
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
H'00
Retained Retained
Retained Retained
Retained Retained
Retained Retained
Retained Retained
Rev. 1.00 Oct. 01, 2007 Page 1028 of 1956
REJ09B0256-0100