SH7763 Datasheet, PDF (1279/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 29 Serial I/O with FIFO (SIOF)
29.3.11 Transmit Data Assign Register (SITDAR)
SITDAR is a 16-bit readable/writable register that specifies the position of the transmit data in a
frame.
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
TDLE — — —
TDLA[3:0]
TDRE TLREP — —
TDRA[3:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R R R R/W R/W R/W R/W R/W R/W R R R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
15
TDLE
0
R/W Transmit Left-Channel Data Enable
0: Disables left-channel data transmission
1: Enables left-channel data transmission
14 to 12 —
All 0 R
Reserved
These bits are always read as 0. The write value
should always be 0.
11 to 8 TDLA[3:0] 0000 R/W Transmit Left-Channel Data Assigns 3 to 0
Specify the position of left-channel data in a transmit
frame as B'0000 (0) to B'1110 (14).
1111: Setting prohibited
• Transmit data for the left channel is specified in the
SITDL bit in SITDR.
7
TDRE
0
R/W Transmit Right-Channel Data Enable
0: Disables right-channel data transmission
1: Enables right-channel data transmission
6
TLREP
0
R/W Transmit Left-Channel Repeat
0: Transmits data specified in the SITDR bit in SITDR
as right-channel data
1: Repeatedly transmits data specified in the SITDL bit
in SITDR as right-channel data
• This bit setting is valid when the TDRE bit is set to
1.
• When this bit is set to 1, the SITDR settings are
ignored.
Rev. 1.00 Oct. 01, 2007 Page 1213 of 1956
REJ09B0256-0100