SH7763 Datasheet, PDF (1268/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 29 Serial I/O with FIFO (SIOF)
29.3.7 Receive Control Data Register (SIRCR)
SIRCR is a 32-bit readable/writable register that stores receive control data of the SIOF. SIRCR
can be specified only when the FL bit in SIMDR is specified as 1xxx (x: don't care.).
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SIRC0[15:0]
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SIRC1[15:0]
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W
31 to 16 SIRC0[15:0] Undefined R/W
15 to 0 SIRC1[15:0] Undefined R/W
Description
Control Channel 0 Receive Data
Store data received from the SIOF_RXD pin as control
channel 0 receive data. The position of the control
channel 0 data in the transmit or receive frame is
specified by the CD0A bit in SICDAR.
• These bits are valid only when the CD0E bit in
SICDAR is set to 1.
Control Channel 1 Receive Data
Store data received from the SIOF_RXD pin as control
channel 1 receive data. The position of the control
channel 1 data in the transmit or receive frame is
specified by the CD1A bit in SICDAR.
• These bits are valid only when the CD1E bit in
SICDAR is set to 1.
Rev. 1.00 Oct. 01, 2007 Page 1202 of 1956
REJ09B0256-0100