SH7763 Datasheet, PDF (243/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 6 Memory Management Unit (MMU)
31
2019
14 13
87
21 0
Address field 1 1 1 1 0 1 1 1 0 0 0 0 _{* * * * * *}
E
* * * * * *0 0
31 29 28
Data field
PPN
10 9 8 7 6 5 4 3 2 1 0
V PR C D
PPN: Physical page number
V: Validity bit
E: Entry
SZ: Page size bits
D: Dirty bit
*: Don't care
PR: Protection key data _SZ1
C: Cacheability bit
SH
WT
SH: Share status bit
WT: Write-through bit
: Reserved bits (write value should be 0
and read value is undefined )
Figure 6.15 Memory-Mapped UTLB Data Array
6.7 32-Bit Address Extended Mode
Setting the SE bit in PASCR to 1 changes mode from 29-bit address mode which handles the 29-
bit physical address space to 32-bit address extended mode which handles the 32-bit physical
address space.
Virtual address space
U0/P0
(2GB)
29-bits
address space
0.5GB
Virtual address space
U0/P0
(2GB)
32-bit
address space
P1(0.5GB)
P2(0.5GB)
P3(0.5GB)
P4(0.5GB)
29-bit Physical address space
(Normal mode)
P1/P2
(1GB)
P3(0.5GB)
P4(0.5GB)
4GB
32-bit Physical address space
(Extended mode)
Figure 6.16 Physical Address Space (32-Bit Address Extended Mode)
Rev. 1.00 Oct. 01, 2007 Page 177 of 1956
REJ09B0256-0100