SH7763 Datasheet, PDF (761/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 19 Timer Unit (TMU)
19.3.3 Timer Constant Register (TCORn) (n = 0 to 5)
The TCOR registers are 32-bit readable/writable registers. When a TCNT counter underflows
while counting down, the TCOR value is set in that TCNT, which continues counting down from
the set value.
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
19.3.4 Timer Counter (TCNTn) (n = 0 to 5)
The TCNT registers are 32-bit readable/writable registers. Each TCNT counts down on the input
clock selected by the TPSC2 to TPSC0 bits in TCR.
When a TCNT counter underflows while counting down, the UNF flag is set in TCR of the
corresponding channel. At the same time, the TCOR value is set in TCNT, and the count-down
operation continues from the set value.
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 1.00 Oct. 01, 2007 Page 695 of 1956
REJ09B0256-0100