SH7763 Datasheet, PDF (1190/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
28.3 Register Descriptions
Table 28.2 shows the SCIF/IrDA register configuration. Table 28.3 shows the register states in
each operating mode.
Table 28.2 Register Configuration
Ch. Register Name
Area 7
Abbrev. R/W P4 Address Address
2 Serial mode register 2
SCSMR2 R/W H'FFE1 0000 H'1FE1 0000
Bit rate register 2
SCBRR2 R/W H'FFE1 0004 H'1FE1 0004
Serial control register 2
SCSCR2 R/W H'FFE1 0008 H'1FE1 0008
Transmit FIFO data register 2 SCFTDR2 W
H'FFE1 000C H'1FE1 000C
Serial status register 2
SCFSR2 R/W*¹ H'FFE1 0010 H'1FE1 0010
Receive FIFO data register 2 SCFRDR2 R
H'FFE1 0014 H'1FE1 0014
FIFO control register 2
SCFCR2 R/W H'FFE1 0018 H'1FE10018
FIFO data count register 2 SCFDR2 R
H'FFE1 001C H'1FE1 001C
Serial port register 2
Line status register 2
SCSPTR2 R/W H'FFE1 0020 H'1FE1 0020
SCLSR2 R/W*² H'FFE1 0024 H'1FE1 0024
BRG frequency division
register
BRGDL2 R/W H'FFE1 0030 H'FFE1 0030
BRG clock select register
BRGCKS2 R/W H'FFE1 0034 H'FFE1 0034
IrDA serial mode register
SCSMRIR R/W H'FFE1 0040 H'FFE1 0040
Notes: 1. To clear the flags, 0s can only be written to bits 7 to 4, 1, and 0.
2. To clear the flag, 0 can only be written to bit 0.
Size
16
8
16
8
16
8
16
16
16
16
16
16
16
Rev. 1.00 Oct. 01, 2007 Page 1124 of 1956
REJ09B0256-0100