SH7763 Datasheet, PDF (1225/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 28 Serial Communication Interface with FIFO/IrDA Interface (SCIF/IrDA)
(4) Serial Data Transmission (Asynchronous Mode):
Figure 28.7 shows a sample flowchart for serial transmission.
Use the following procedure for serial data transmission after enabling the SCIF for transmission.
Start of transmission
Read TDFE flag in SCFSR
No
TDFE = 1?
Yes
Write transmit data in SCFTDR
No
All data transmitted?
Yes
Read TEND flag in SCFSR
No
TEND = 1?
Yes
No
Break output?
Yes
Clear SPB2DT to 0 and
set SPB2IO to 1
[1] SCIF status check and transmit data write:
Read SCFSR and check that the TDFE flag is set to 1,
then write transmit data to SCFTDR, and clear the TDFE
and TEND flags to 0.
The number of transmit data bytes that can be written is
16 - (transmit trigger set number).
[2] Serial transmission continuation procedure:
[1]
To continue serial transmission, read 1 from the TDFE flag
to confirm that writing is possible, then write data to SCFTDR,
and then clear the TDFE flag to 0.
[2]
[3] Break output at the end of serial transmission:
To output a break in serial transmission, clear the SPB2DT
bit to 0 and set the SPB2IO bit to 1 in SCSPTR, then clear
the TE bit in SCSCR to 0.
In [1] and [2], it is possible to ascertain the number of data
bytes that can be written from the number of transmit data
bytes in SCFTDR indicated by SCFDR.
[3]
Clear TE bit in SCSCR to 0
End of transmission
Figure 28.7 Sample Serial Transmission Flowchart
Rev. 1.00 Oct. 01, 2007 Page 1159 of 1956
REJ09B0256-0100