SH7763 Datasheet, PDF (1570/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 36 USB Function Controller (USBF)
36.3.1 Interrupt Flag Register 0 (IFR0)
IFR0 is an interrupt flag register for EP0i, EP1, EP2, bus reset, and setup command reception.
When each flag is set to 1 and interrupt is enabled in the corresponding bit of IER0, an interrupt
request (USBF10 or USB11) specified by the corresponding bit in ISR0 is issued to INTC.
Clearing the flag is performed by writing 0. Writing 1 is not valid and nothing is changed. To clear
bits, access the register so that 0 should be only to the bits for the interrupt sources to be cleared
and that 1 should be written to the other bits. Do not use a bit field declaration of the C language
to clear bits.
EP2 EMPTY and EP1 FULL are status bits that indicate the FIFO states of EP1 and EP2,
respectively. Therefore, EP2 EMPTY and EP1 FULL cannot be cleared.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: — — — — — — — — — — — — — — — —
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
—
BRST
EP1
FULL
EP2 EP2 SETUP EP0O EP0I
TR EMPTY TS TS TR
EP0I
TS
Initial value: — — — — — — — — 0
0
0
1
0
0
0
0
R/W: R R R R R R R R R/W R R/W R R/W R/W R/W R/W
Bit
Bit Name Initial Value
31 to 8 
Undefined
7
BRST
0
R/W Description
R Reserved
These bits are always read as undefined value. Write
value should always be 0.
R/W Bus Reset
[Setting condition]
When a bus reset signal is detected on the USB bus.
[Clearing conditions]
• When reset
• When 0 is written to by CPU
Rev. 1.00 Oct. 01, 2007 Page 1504 of 1956
REJ09B0256-0100