SH7763 Datasheet, PDF (604/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
To access the address space of this LSI, use the PCI memory base address register
(PCIMBAR0/1), PCI local space register (PCILSR0/1), and PCI local address register
(PCILAR0/1). The address spaces are mapped by software. The PCIC includes two memory
mapping registers.
Setting these two registers enables the use of two spaces.
The size of these address spaces are selectable from 1 Mbyte to 512 Mbytes by setting the PCI
local space register (PCILSR0/1).
Single longword and burst transfers are supported for the memory data transfer to a PCI target.
A certain range of the address space on the PCI local bus corresponds to the local address space on
the SuperHyway bus. The local address space 0 is controlled by the PCIMBAR0, PCILSR0 and
PCILAR0. And the local address space 1 is controlled by the PCIMBAR1, PCILSR1 and
PCILAR1. Figure 13.10 shows the method of accessing the local address space.
The PCIMBAR0/1 indicates the starting address of the memory space used by the PCI device. The
PCILAR0/1 specifies the starting address of the local address space 0/1. The PCILSR0/1
expresses the size of the memory used by the PCI device.
Address translation from PCI local bus to SuperHyway bus
For the PCIMBAR0/1 and PCILAR0/1, the more significant address bits that are higher than the
memory size set in the PCILSR0/1 becomes valid. The more significant address bits of the
PCIMBAR0/1 and the same field line bits of the PCI local bus address output from an external
PCI device are compared for the purpose of determining whether the access is made to the PCIC.
When the addresses correspond, the access to the PCIC is recognized, and a local address is
generated from the more significant address bits of the PCILAR0/1 and the less significant bits of
the PCI local bus address output from the external PCI device. The PCI command is executed for
this local address.
If the more significant address bits of the PCI local bus address output from the external PCI
device does not correspond with the more significant address bits of the PCIMBAR0/1, the PCIC
does not respond to the PCI command.
Note: In the following figures, “SH” means the SuperHyway bus of this LSI and “PCI” means
the PCI local bus.
Rev. 1.00 Oct. 01, 2007 Page 538 of 1956
REJ09B0256-0100