SH7763 Datasheet, PDF (1595/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 36 USB Function Controller (USBF)
36.3.20 EP2 Data Register (EPDR2)
EPDR2 is a 128-byte transmit FIFO buffer for endpoint 2. EPDR2 has a dual-buffer configuration,
and has a capacity of twice the maximum packet size. When transmit data is written to this FIFO
buffer and EP2PKTE in the trigger register is set, one packet of transmit data is fixed, and the
dual-FIFO buffer is switched over. Transmit data for this FIFO buffer can be transferred by DMA.
This FIFO buffer can be initialized by means of EP2CLR in the FCLR0 register.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: — — — — — — — — — — — — — — — —
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
————————
D[7:0]
Initial value: — — — — — — — — — — — — — — — —
R/W: R R R R R R R R W W W W W W W W
Bit
Bit Name
31 to 8 
7 to 0 D[7:0]
Initial Value R/W Description
Undefined R Reserved
These bits are always read as undefined value.
Write value should always be 0.
Undefined W Data register for endpoint 2 transfer
Rev. 1.00 Oct. 01, 2007 Page 1529 of 1956
REJ09B0256-0100