SH7763 Datasheet, PDF (1730/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 38 A/D Converter
ADST
ADF
ADI
Channel 0(AN0)
Set*
Clear*
Interrupt occurs
Idle
Set*
Clear*
Channel 1(AN1) Idle
A/D conversion (1)
Idle
A/D conversion (2)
Idle
Channel 2(AN2)
Idle
Channel 3(AN3)
Idle
ADDRA
ADDRB
Read result
A/D conversion result (1)
Read result
A/D conversion result (2)
ADDRC
ADDRD
Note: * Vertical arrows (↓) indicate instruction execution by software.
Figure 38.2 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
38.4.2 Multi Mode (MDS[1:0] = 10)
In multi mode, analog inputs for the specified channels (one or more) are converted once each.
A/D conversion starts with the first channel (AN0) when the ADST bit (bit 13) of the A/D
control/status register (ADCSR) is set to 1 by software.
When multiple channels are selected, A/D conversion for the second channel (AN1) starts
immediately after A/D conversion for the first channel ends.
A/D conversion on the specified channels is performed for one cycle. The conversion results are
transferred for storage to the ADDR that corresponds to the channel.
When setting the A/D control/status register (ADCSR) or switching the analog input channel
during A/D conversion, first clear the ADST bit to 0 to halt A/D conversion in order to avoid
malfunction. After the change has been made, setting the ADST bit to 1 selects the first channel
and A/D conversion is resumed.
Rev. 1.00 Oct. 01, 2007 Page 1664 of 1956
REJ09B0256-0100