SH7763 Datasheet, PDF (299/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 9 Interrupt Controller (INTC)
Section 9 Interrupt Controller (INTC)
The interrupt controller (INTC) determines the priority of interrupt sources and controls interrupt
requests to the CPU (SH-4A). The INTC has a register that sets the priority of each interrupt and
interrupt requests are processed according to the priority set in this register by the user.
9.1 Features
SH-4 compatible specifications
• Fifteen levels of external interrupt priority can be set
By setting the interrupt priority registers, the priorities of external interrupts can be selected
from 15 levels for individual request sources.
• NMI noise canceller function
An NMI input-level bit indicates the NMI pin state. By reading this bit in the interrupt
exception handling routine, the pin state can be checked, enabling it to be used as a noise
canceller.
• NMI request masking when the block bit (BL) in the status register (SR) is set to 1
Whether to mask NMI requests when the BL bit in SR is set to 1 can be selected.
Extended function for SH-4A
• Automatically updates the IMASK bit in SR according to the accepted interrupt level
• Thirteen levels of on-chip module interrupt priority can be set
By setting thirteen interrupt priority registers, the priorities of on-chip module interrupts can be
selected from 30 levels for individual request sources.
• User-mode interrupt disabling function
Specifying an interrupt mask level in the user interrupt mask level register (USERIMASK)
disables interrupts which are not higher in priority than the specified mask level in user mode.
Figure 9.1 shows a block diagram of the INTC.
Rev. 1.00 Oct. 01, 2007 Page 233 of 1956
REJ09B0256-0100