SH7763 Datasheet, PDF (1067/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 25 Stream Interface (STIF)
Table 25.3 Register States in Each Operating Mode
Register Name
Abbrevia- Power-On Manual
tion
Reset
Reset
Sleep Standby
Mode register 0
STIMDR0 H'00000000 H'00000000 Retained Retained
Control register 0
STICR0 H'00000000 H'00000000 Retained Retained
Interrupt status register 0
STIISR0 H'00000000 H'00000000 Retained Retained
Interrupt enable register 0
STIIER0 H'00000000 H'00000000 Retained Retained
Time stamp counter register 0
STITSC0 H'00000000 H'00000000 Retained Retained
Transmit/receive packet count
register 0
STIPNR0 H'00000000 H'00000000 Retained Retained
Transmit/receive packet counter
register 0
STIPCR0 H'00000000 H'00000000 Retained Retained
Transmit/receive FIFO data register 0 STIFIFO0 H'00000000 H'00000000 Retained Retained
Mode register 1
STIMDR1 H'00000000 H'00000000 Retained Retained
Control register 1
STICR1 H'00000000 H'00000000 Retained Retained
Interrupt status register 1
STIISR1 H'00000000 H'00000000 Retained Retained
Interrupt enable register 1
STIIER1 H'00000000 H'00000000 Retained Retained
Time stamp counter register 1
STITSC1 H'00000000 H'00000000 Retained Retained
Transmit/receive packet count
register 1
STIPNR1 H'00000000 H'00000000 Retained Retained
Transmit/receive packet counter
register 1
STIPCR1 H'00000000 H'00000000 Retained Retained
Transmit/receive FIFO data register 1 STIFIFO1 H'00000000 H'00000000 Retained Retained
Rev. 1.00 Oct. 01, 2007 Page 1001 of 1956
REJ09B0256-0100