SH7763 Datasheet, PDF (258/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 7 Caches
Bit
10, 9
8
7 to 4
3
2
1
Bit Name

Initial
Value
All 0
ICE
0

All 0
OCI
0
CB
0
WT
0
R/W Description
R
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
R/W IC Enable Bit
Selects whether the IC is used. Note however when
address translation is performed, the IC cannot be used
unless the C bit in the page management information is
also 1.
0: IC not used
1: IC used
R
Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
R/W OC Invalidation Bit
When 1 is written to this bit, the V and U bits of all OC
entries are cleared to 0. This bit is always read as 0.
R/W Copy-Back Bit
Indicates the P1 area cache write mode.
0: Write-through mode
1: Copy-back mode
R/W Write-Through Mode
Indicates the P0, U0, and P3 area cache write mode.
When address translation is performed, the value of the
WT bit in the page management information has
priority.
0: Copy-back mode
1: Write-through mode
Rev. 1.00 Oct. 01, 2007 Page 192 of 1956
REJ09B0256-0100