SH7763 Datasheet, PDF (1055/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.5.4 Accessing MII Registers
MII registers in the PHY-LSI are accessed via PIR in this LSI. PIR is used as a serial interface
conforming to the MII frame format specified in IEEE802.3u.
(1) MII Management Frame Format
Figure 23.32 shows the format of an MII management frame. To access an MII register, a
management frame is implemented by the program in accordance with the procedures shown in
MII Register Access Procedure.
Access Type
Item
PRE
ST
Number of bits 32
2
Read
1..1
01
Write
1..1
01
MII Management Frame
OP
PHYAD REGAD
TA
2
5
5
2
10
00001 RRRRR
Z0
01
00001 RRRRR
10
DATA
16
D..D
D..D
[Legend]
PRE: 32 consecutive 1s
ST:
Write of 01 indicating start of frame
OP:
Write of code indicating access type
PHYAD: Write of 0001 if the PHY-LSI address is 1 (sequential write starting with the MSB).
This bit changes depending on the PHY-LSI address.
REGAD: Write of 000q if the register address is 1 (sequential write starting with the MSB).
This bit changes depending on the PHY-LSI register address.
TA:
Time for switching data transmission source on MII interface
(a) Write: 10 written
(b) Read: Bus release (notation: Z0) perdormed
DATA: 16-bit data. Sequential write or read from MSB
(a) Write: 16-bit data write
(b) Read: 16-bit data read
IDLE: Wait time until next MII management format input
(a) Write: Independent bus release (notation: X) performad
(d) Read: Bus already released in TA: control unnecessary
Figure 23.32 MII Management Frame Format
IDLE
X
Rev. 1.00 Oct. 01, 2007 Page 989 of 1956
REJ09B0256-0100