SH7763 Datasheet, PDF (1052/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.5.2 GMII/MII Frame Reception Timing
Each GMII/MII frame reception timing is shown in figures 23.23 to 23.28.
ET_RX-CLK
ET_RX-DV
GET_ERXD7 to 4
ET_ERXD3 to 0
ET_RX-ER
ET_RX-CRS
Preamble SFD
Data
CRC
Figure 23.23 GMII/MII Fame Receive Timing (Normal Reception)
ET_RX-CLK
ET_RX-DV
GET_ERXD7 to 4
ET_ERXD3 to 0
CRC
0F
ET_RX-ER
ET_RX-CRS
Figure 23.24 GMII/MII Fame Receive Timing (with Carrier Extension)
ET_RX-CLK
ET_RX-DV
GET_ERXD7 to 4
ET_ERXD3 to 0
ET_RX-ER
ET_RX-CRS
CRC
0F
Preamble
Figure 23.25 GMII/MII Fame Receive Timing (Burst Reception)
Rev. 1.00 Oct. 01, 2007 Page 986 of 1956
REJ09B0256-0100