SH7763 Datasheet, PDF (492/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 12 DDR-SDRAM Interface (DDRIF)
Initial
Bit
Bit Name Value R/W Description
1
SRCD
0
R/W Number of Cycles between RAS and CAS Commands
Specifies the number of cycles from RAS (ACT)
command issuance to CAS (READ/READA,
WRITE/WRITEA) command issuance (Trcd).
0: 3 cycles
1: 4 cycles
0
SRP
0
R/W Number of Cycles between PRE and ACT Commands
Specifies the number of cycles from PRE command
issuance to ACT command issuance (Trp).
0: 3 cycles
1: 4 cycles
12.4.4 DDR-SDRAM Row Attribute Register (SDR)
Bit:
63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 47
Initial value:
R/W:
Bit:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RRRRRRRRRRRRRRRR
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
Initial value:
R/W:
Bit:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RRRRRRRRRRRRRRRR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value:
R/W:
Bit:
Initial value:
R/W:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
RRRRRRRRRRRRRRRR
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SPLIT
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
R R R R R/W R/W R/W R/W R R R R R R R R
Rev. 1.00 Oct. 01, 2007 Page 426 of 1956
REJ09B0256-0100