SH7763 Datasheet, PDF (1295/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 29 Serial I/O with FIFO (SIOF)
29.4.7 Transmit and Receive Procedures
(1) Transmission in Master Mode
Figure 29.9 shows an example of settings and operation for master mode transmission.
No.
Flow Chart
Start
1
Set SIMDR, SISCR, SITDAR,
SICDAR, SITCR, and SIFCTR
2
Set the SCKE bit in SICTR to 1
3
Start SIOF_SCK output
SIOF Settings
SIOF Operation
Set operating mode, serial clock,
slot positions for transmit data,
slot position for control data,
control data, and FIFO request
threshold value
Set operation start for baud rate
generator
Output serial clock
4
Set the FSE and TXE bits
in SICTR to 1
Set the start for frame synchronous Output frame synchronous
signal output and enable transmission signal and issue transmit
transfer request*
5
TDREQ = 1? ^No
Yes
6
Set SITDR
Set transmit data
7
Transmit SITDR from SIOF_TXD
synchronously with SIOF_SYNC
Transmit
Transfer
No
ended?
8
Yes
Clear the TXE bit in SICTR to 0
Set to disable transmission
End transmission
End
Note: * When interrupts due to transmit data underflow are enabled, after setting the no. 6 transmit data, the
TXE bit should be set to 1.
Figure 29.9 Example of Transmit Operation in Master Mode
Rev. 1.00 Oct. 01, 2007 Page 1229 of 1956
REJ09B0256-0100