SH7763 Datasheet, PDF (1312/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 30 SIM Card Module (SIM)
30.3.1 Serial Mode Register (SCSMR)
SCSMR is an 8-bit readable/writable register that selects settings for the communication format of
the smart card interface.
Bit: 7
6
5
4
3
2
1
0
− − − ^{PE O/E} − − −
Initial value: 0
0
1
0
0
0
0
0
R/W: R
R
R R/W R
R
R
R
Initial
Bit
Bit Name Value R/W Description
7, 6 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
5
PE
1
R
Parity Enable
This bit is always read as 1. The write value should
always be 1.
4
O/E
0
R/W Parity Mode
Selects whether even or odd parity is to be used when
adding a parity bit and checking parity.
0: Even parity*¹
1: Odd parity*²
Notes: 1. When set to even parity, during transmission a
parity bit is added such that the sum of 1 bits in
the parity bit and transmit characters is even.
During reception, a check is performed to
ensure that the sum of 1 bits in the parity bit
and the receive characters is even.
2. When set to odd parity, during transmission a
parity bit is added such that the sum of 1 bits in
the parity bit and transmit characters is odd.
During reception, a check is performed to
ensure that the sum of 1 bits in the parity bit
and the receive characters is odd.
3 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Oct. 01, 2007 Page 1246 of 1956
REJ09B0256-0100