SH7763 Datasheet, PDF (1576/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 36 USB Function Controller (USBF)
Bit Bit Name Initial Value R/W Description
4
SURSF 0
R/W Suspend/Resume Detection
[Setting condition]
When the bus transits from the normal state to the
suspend state or from the suspend state to the normal
state.
[Clearing conditions]
• When reset
• When 0 is written to by CPU
3
CFDN
0
R/W End Point Information Load Complete
[Setting condition]
When the end point information written in EPIR is
completed to be set (loaded) in this controller.
Note: This controller operates normally as USB after
the setting of the end point information is
completed.
[Clearing conditions]
• When reset
• When 0 is written to by CPU
2
SOF
0
R/W SOF Packet
[Setting condition]
When the valid SOF packet is detected.
[Clearing conditions]
• When reset
• When 0 is written to by CPU
1
SETC
0
R/W Set Configuration Command Detection
[Setting condition]
When the valid Set Configuration command is
detected.
[Clearing conditions]
• When reset
• When 0 is written to by CPU
Rev. 1.00 Oct. 01, 2007 Page 1510 of 1956
REJ09B0256-0100