SH7763 Datasheet, PDF (1964/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 43 Electrical Characteristics
43.4.23 H-UDI Module Signal Timing
Table 43.38 H-UDI Module Signal Timing
Conditions:
V_CCQ = VDD_RTC = AV_CC = 3.0 to 3.6 V, V_CCQ-DDR = 2.3 to 2.7 V, VDD = 1.15 to
1.35 V, Ta = −20 to 75°C
Item
Input clock cycle
Input clock pulse width (High)
Input clock pulse width (Low)
Input clock rise time
Input clock fall time
ASEBRK setup time
ASEBRK hold time
TDI/TMS setup time
TDI/TMS hold time
TDO data delay time
ASEBRK pin break pulse width
Notes: 1. t : One CLKOUT cycle time
cyc
2. t : One Pck0 cycle time
Pcyc0
Symbol
t
TCKcyc
t_TCKH
t_TCKL
t
TCKr
t
TCKf
t
ASEBRKS
t
ASEBRKH
t_TDIS
t
TDIH
t_TDO
t_PINBRK
Min.
50
15
15
—
—
10
10
15
15
0
2
Max.
—
—
—
10
10
—
—
—
—
10
—
Unit
ns
ns
ns
ns
ns
t
cyc
t
cyc
ns
ns
ns
t_Pcyc0
Figure
43.81, 43.83
43.81
43.81
43.81
43.81
43.82
43.82
43.83
43.83
43.83
43.84
t_TCKcyc
t_TCKH
t_TCKL
TCK 1/2V_CCQ
V_IH
V_IH
V_IL
V_IL
t_TCKf
V_IH
1/2V_CCQ
t_TCKr
Note: When clock is input from TCK pin.
Figure 43.81 TCK Input Timing
Rev. 1.00 Oct. 01, 2007 Page 1898 of 1956
REJ09B0256-0100