SH7763 Datasheet, PDF (605/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 13 PCI Controller (PCIC)
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PCI address
SH address
compare
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PCIMBAR0/1
MBA (upper)
PCILAR0/1
LAR
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PCILSR0/1
0 0 0 001 100
10
0 0/1
Figure 13.10 PCI Local Bus to SuperHyway Bus Address Translation
(Local Address Space 0/1)
When all the MBARE bits in PCILSR0/1 are 0, the PCI local bus address is sent to the
SuperHyway bus without translation.
Data prefetching for memory read commands is supported. When a PCI burst read is performed, 8
bytes, or 32 bytes of data block is prefetched. (this depends on the settings of the PFE and PFCS
bits in PCICR).
(2) Accessing PCIC I/O Space
Allocate a 256-byte area to the I/O address space.
Address translation from PCI local bus to SuperHyway bus
The lower 8 bits ([7:0]) are sent to the SuperHyway bus without translation.
When bits 31 to 8 of a PCI local bus address match bits 31 to 8 in a PCI I/O base address register
(PCIIBAR), the upper 24 bits of a PCI local bus address are replaced with H'FE04 01.
Rev. 1.00 Oct. 01, 2007 Page 539 of 1956
REJ09B0256-0100