SH7763 Datasheet, PDF (1043/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
Interrupt Interrupt Source
Transmit/
receive
interrupt for
port 1
(GEINT1)
Transmit Retry Over
Receive Multicast Address Frame
Carrier Extension Error
Carrier Extension Loss
Receive Residual-Bit Frame
Receive Too-Long Frame
Receive Too-Short Frame
PHY-LSI Receive Error
CRC Error on Received Frame
Interrupt with Port 0-to-1 Transfer FIFO Overflow
transfer
Detect
between port _{E-MAC-0 Overflow Alert Signal Output}
0 and port 1
(GEINT2)
E-MAC-0 Carrier Extension Loss Error
Detect
E-MAC-0 Residual-Bit Frame Receive
E-MAC-0 Too-Long Frame Receive
E-MAC-0 Too-Short Frame Receive
E-MAC-0 Frame Receive Error
E-MAC-0 CRC Error Frame Receive
Port 1-to-0 Transfer FIFO Overflow
Detect
E-MAC-1 Overflow Alert Signal Output
E-MAC-1 Carrier Extension Loss Error
Detect
E-MAC-1 Residual-Bit Frame Receive
Register and Bit
Interrupt
Generated Timing
EESR1.TRO
When the interrupt
source is detected
EESR1.RMAF
After write-back
EESR1.CEEF
After write-back
EESR1.CELF
After write-back
EESR1.RRF
After write-back
EESR1.RTLF
After write-back
EESR1.RTSF
After write-back
EESR1.PRE
After write-back
EESR1.CERF
After write-back
TSU_FWSR.OVF0 When the interrupt
source is detected
TSU_FWSR.RBSY0 When the interrupt
source is detected
TSU_FWSR.RINT60 When the interrupt
source is detected
TSU_FWSR.RINT50 When the interrupt
source is detected
TSU_FWSR.RINT40 When the interrupt
source is detected
TSU_FWSR.RINT30 When the interrupt
source is detected
TSU_FWSR.RINT20 When the interrupt
source is detected
TSU_FWSR.RINT10 When the interrupt
source is detected
TSU_FWSR.OVF1 When the interrupt
source is detected
TSU_FWSR.RBSY1 When the interrupt
source is detected
TSU_FWSR.RINT61 When the interrupt
source is detected
TSU_FWSR.RINT51 When the interrupt
source is detected
Rev. 1.00 Oct. 01, 2007 Page 977 of 1956
REJ09B0256-0100