SH7763 Datasheet, PDF (705/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 16 Clock Pulse Generator (CPG)
16.4.1 Frequency Control Register (FRQCR)
FRQCR is a 32-bit read-only register used to confirm the division ratios for the CPU clock (Ick),
SHwy clock (SHck), peripheral clocks (Pck0, Pck1), and the bus clock (Bck) after a power-on
reset. For the frequency ratios, refer to table 16.2, Clock Operating Modes. This register can be
accessed only in longwords. Operation cannot be guaranteed if this register is written to.
FRQCR is only initialized by a power-on reset caused by the PRESET pin or watchdog timer
overflow.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
      
CFC[2:0]

BFC[2:0]
Initial value: 0
00
1
0
0
0
0
0
0
0
1
0
0
1
1
R/W: R R R R/W R/W R/W R/W R/W R R R R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
      
Initial value: 0 0
0
0000
00
R/W: R R R R/W R/W R/W R/W R/W R
6
5
4
P0FC[2:0]
0
1
1
R R R/W
3

0
R/W
2
1
0
P1FC[2:0]
1
0
1
R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 28 —
0001 R
Reserved
These bits are read as B'0001.
27 to 23 —
All 0 R
Reserved
These bits are always read as all 0.
22 to 20 CFC[2:0] 001
R
CPU Clock (Ick) and SHwy Clock (SHck) Frequency
Division Ratios
CFC[2:0] Ick SHck
001:
×1/2 ×1/4
19
—
0
R
Reserved
This bit is always read as 0.
18 to 16 BFC[2:0] 011
R
Bus Clock 0 (Bck) Frequency Division Ratio
011: ×1/8
15 to 7 —
All 0 R
Reserved
These bits are always read as all 0.
6 to 4 P0FC[2:0] 011
R
Peripheral Clock 0 (Pck0) Frequency Division Ratio
011: ×1/8
Rev. 1.00 Oct. 01, 2007 Page 639 of 1956
REJ09B0256-0100