SH7763 Datasheet, PDF (976/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 23 Gigabit Ethernet Controller (GETHER)
23.3.74 E-MAC/E-DMAC Status Register (EESR)
EESR is a 32-bit readable/writable register that shows communications status information on the
E-DMAC in combination with the E-MAC. The information in this register is reported in the form
of interrupt sources. Individual bits are cleared by writing 1 (however, bit 22 (ECI) is a read-only
bit that is not cleared by writing 1) and are not affected by writing 0. Each interrupt source can
also be masked by means of the corresponding bit in the E-MAC/E-DMAC status interrupt
permission register (EESIPR).
The interrupts generated by this status register are GEINT0 for port 0 and GEINT1 for port 1. For
interrupt priorities, see section 9.4.6, Interrupt Exception Handling and Priority in section 9,
Interrupt Controller (INTC). GEINT2 is an interrupt generated by TSU_FWSR in the TSU.
Bit: 31 30 29 28 27 26 25 24 23
TWB[1:0] TC[1] TUC ROC TABT RABT RFCOF 
Initial value: 0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R
22 21 20 19 18 17 16
ECI TC[0] TDE TFUF FR RDE RFE
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0




 DLC CD TRO RMAF CEEF CELF RRF RTLF RTSF PRE CERF
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
31, 30
Bit Name
TWB[1:0]
Initial
Value
00
R/W Description
R/W Write-Back Complete
Indicates that write-back from the E-DMAC to the
corresponding descriptor after frame transmission has
completed. This operation is enabled only when the
TWBI bit in the transmit descriptor that includes the end
of the transmit frame is set to 1.
00: Write-back has not completed, or no transmission
directive
11: Write-back has completed
Others: Setting disabled
Rev. 1.00 Oct. 01, 2007 Page 910 of 1956
REJ09B0256-0100