SH7763 Datasheet, PDF (1853/2026 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC Engine Family SH-4A Series

Section 41 User Break Controller (UBC)
41.3.5 Sequential Break
1. Sequential break conditions can be specified by setting the MFE and MFI bits in the match
condition setting registers (CBR0 and CBR1). (Sequential break involves two cases such that
channel 0 break condition is satisfied then channel 1 break condition is satisfied, and vice
versa.) To use the sequential break function, clear the MFE bit of the match condition setting
register and the BIE bit of the match operation setting register of the first channel in the
sequence, and set the MFE bit and specify the number of the second channel in the sequence
using the MFI bit in the match condition setting register of the second channel in the sequence.
If the sequential break condition is set, the condition match flag is set every time the match
condition is satisfied for each channel. When the condition has been satisfied for the first
channel in the sequence but not for the second channel in the sequence, clear the condition
match flag for the first channel in the sequence in order to release the first channel in the
sequence from the match state.
2. For channel 1, the execution count break condition can also be included in the sequential break
conditions.
3. If the match conditions for the first and second channels in the sequence are satisfied within a
significantly short time, sequential operation may not be guaranteed in some cases, as shown
below.
• When the Match Condition is Satisfied at the Instruction Fetch Cycle for Both the First and
Second Channels in the Sequence:
Instruction B is 0 instruction after instruction A Equivalent to setting the same addresses; do
not use this setting.
Instruction B is one instruction after instruction A Sequential operation is not guaranteed.
Instruction B is two or more instructions after
instruction A
Sequential operation is guaranteed.
• When the match condition is satisfied at the instruction fetch cycle for the first channel in the
sequence whereas the match condition is satisfied at the operand access cycle for the second
channel in the sequence:
Instruction B is 0 or one instruction after
instruction A
Instruction B is two or more instructions after
instruction A
Sequential operation is not guaranteed.
Sequential operation is guaranteed.
Rev. 1.00 Oct. 01, 2007 Page 1787 of 1956
REJ09B0256-0100